microsoft-windows-hal-events.dll
Associated Error Codes
Below lists error codes and symbolic names found for this module.
| Code | Found in | Description |
|---|---|---|
| 0x1 | 1011 | Initialization of the High Precision Event Timer failed due to a BIOS configuration problem. The operating system will use another available platform timer in lieu of the High Precision Event Timer. Contact your system vendor for technical assistance. Initialization status: %1. |
| 0x2 | 1011 | Initialization of the High Precision Event Timer failed due to unsupported hardware. The operating system will use another available platform timer in lieu of the High Precision Event Timer. Initialization status: %1. |
| 0x3 | 1011 | Initialization of the High Precision Event Timer failed due to an interrupt configuration problem. The operating system will use another available platform timer in lieu of the High Precision Event Timer. It may be possible to address this problem with an updated system BIOS. Contact your system vendor for technical assistance. Initialization status: %1. |
| 0x4 | 1011 | Due to an unexpected condition, the operating system will use another available platform timer in lieu of the processor's cycle counters. Status: %1. |
| 0xb | 1011 | The High Precision Event Timer failed to deliver message signalled interrupts. The operating system will fall back to line based interrupts for this timer. Initialization status: %1. |
| 0xc | 1011 | The platform firmware has corrupted memory across the previous system power transition. Please check for updated firmware for your system. |
| 0xd | 1011 | The system watchdog timer was triggered. |
| 0xf | 10 | The iommu has detected an error. |
| 0x10 | 10 | The iommu fault reporting has been initialized. |
| 0x50000002 | 1011 | Error |
| 0x50000003 | 1011 | Warning |
| 0x50000004 | 1011 | Information |
| 0x50000005 | 1011 | Verbose |
| 0x90000001 | 1011 | Microsoft-Windows-HAL |
| 0x90000002 | 1011 | System |
| 0x90000003 | 1011 | Microsoft-Windows-HAL/Debug |
| 0xb0000005 | 1011 | Due to an expected condition, the operating system will use another available platform timer in lieu of the processor's cycle counters. Status: %1. |
| 0xb0000007 | 1011 | The processor cycle counter on processor %2 has been probed by processor %1. A counter delta of %3 was detected. The approximate communication delay between these processors was detected to be %4. |
| 0xb0000008 | 1011 | The processor's cycle counters have been successfully synchronized from processor %1 within acceptable operating thresholds. The maximum positive delta detected was %3 and the maximum negative delta was %4. Synchronization executed for %5 microseconds. |
| 0xb0000009 | 1011 | The processor cycle counter on processor %2 was synchronized against processor %1 using an adjustment of %4 cycles on attempt %5. This resulted in a delta of %3 cycles. |
| 0xb000000a | 1011 | The synchronization of the processor's cycle counters was not able to synchronize the processors within acceptable operating thresholds. Status: %1. |
| 0xb000000e | 1011 | The watchdog wake timer was triggered. |
| 0xf | 11 | The IOMMU has detected an error. Device: %1 FaultInformation: %2 FaultReason: %3 ExtendedData: %4 |
| 0x10 | 11 | IOMMU fault reporting has been initialized. |
| 0x11 | 11 | The clock interrupt is backed by a platform timer instead of a per-processor source. System performance may be degraded. |
| 0x12 | 11 | The performance counter is not readable from user mode. System performance may be degraded. |
| 0x13 | 11 | DMA API failure detected. APIIndex: %1 ErrorCode: %2 FailureInformation1: %3 FailureInformation2: %4 |
| 0x14 | 11 | The hardware real-time clock was not queried because evaluation of the ACPI Time and Alarm Device method failed. Status: %1. |
| 0x15 | 11 | The hardware real-time clock was not set because evaluation of the ACPI Time and Alarm Device method failed. Status: %1. |
| 29 entries | ||